Private Line Emulation over Packet Switched Networks
Extracted elements (30)
For 200GBASE-R and 400GBASE-R, rate compensation is applied so the 66B-encoded bit-stream carried by PLE runs at 528/544 times the nominal PMA interface bitrate. Rate compensation blocks are 66B control characters of type 0x00, inserted at a defined rate (X=16 for 200GBASE-R, X=32 for 400GBASE-R) so the CE-bound IWF can identify and strip them.
PLE provides a layer network independent of and beneath SONET/SDH, allowing add/drop multiplexers and cross-connects to be interconnected without the PE interfering with multiplexing structures. This is a key distinction from Circuit Emulation over Packet (CEP, RFC 4842), which operates at the same level as SONET/SDH and performs per-SPE/VT/VC multiplexing and demultiplexing.
The default replacement data value of 0xAA (alternating 0s and 1s) was chosen because it maintains clock synchronization during packet loss and, for 64B/66B code-based services, ensures no invalid sync headers (which would have a sync header value of 11) are generated by the replacement pattern.
The RTP header is reused (not designed from scratch) to align with other bit-stream emulation pseudowires (SAToP RFC 4553, CESoPSN RFC 5086, CEP RFC 4842) and to allow PLE implementations to reuse preexisting work. Full RTP topologies, RTCP, SRTP, header extensions, and CSRC lists are explicitly not supported as they are not applicable to PLE VPWS.
Energy Efficient Ethernet (EEE) deep sleep mode is incompatible with PLE because it causes the CE to cease transmission entirely. Consequently, LPI is not supported for 10GBASE-R services across PLE. For 25GBASE-R and higher services, only fast wake mode is applicable and LPI is supported because the CE transmits /LI/ code blocks instead of stopping.
Fibre Channel speed negotiation is not supported by PLE. Both attachment circuits of the VPWS must be of the same service type and must use the same PLE payload type and payload size, enforced via manual configuration or signaling protocol mechanisms.
A bit-stream is mapped into PLE packets with a fixed payload size that MUST be defined during VPWS setup, MUST be the same in both directions of the VPWS, and MUST remain unchanged for the lifetime of the VPWS. All PLE implementations MUST support the default payload size of 1024 bytes; the minimum is 64 bytes.
A de-jitter buffer MUST be implemented at the CE-bound IWF where PLE packets are stored upon arrival. Lost or dropped packet payloads MUST be replaced with an equivalent amount of replacement data; all PLE implementations MUST support generation of '0xAA' as default replacement data.
For 10GBASE-R and 25GBASE-R, if an optional FEC layer is present, the PSN-bound NSP function MUST terminate the FEC and the CE-bound NSP function MUST generate the FEC. The CE-bound NSP MUST perform PCS code sync, descrambling, and MUST scramble the 64B/66B code stream before sending to the CE.
For OTN services, the PSN-bound NSP function MUST terminate the FEC and replace the OTUk overhead in row 1, columns 8–14 with an all-zeros pattern, producing an extended ODUk frame. The frame alignment overhead (row 1, columns 1–7) is kept as-is.
For SRv6 encapsulation via H.Encaps.L1 or H.Encaps.L1.Red, the next header field of the SRH or last extension header MUST be set to 147 (BIT-EMU). The End.DX1 SID MUST be the last segment in an SR Policy.
Performance monitoring data MUST be provided by the management interface; faults MUST be timestamped when declared and cleared. Fault and performance data SHOULD also be provided by a YANG data model (model specification is out of scope).
The CE-bound IWF enters PLOS state if it detects loss of consecutive packets for a preconfigured time (default 1 millisecond). While in PLOS, the CE-bound NSP MUST inject the appropriate downstream fault-indication signal, and the PSN-bound IWF SHOULD set the R bit in every transmitted PLE packet.
The LEN field in the PLE control word MUST always be set to zero because no padding is added. If the actual packet size is inconsistent with the expected payload size defined in Section 6, the packet MUST be considered malformed.
The PLE header MUST contain a 4-byte PLE control word and MUST include a fixed-size RTP header; the RTP header MUST immediately follow the PLE control word.
The RTP version field MUST be set to 2. The RTP timestamp clock MUST be 125 MHz for bit-streams up to 200 Gbps, and MUST be 250 MHz for bit-streams above 200 Gbps, based on the common clock I.
The total size of a PLE packet for a specific PW MUST NOT exceed the path MTU between the pair of PEs terminating that PW.
When using a 16-bit sequence number space, the RTP sequence number MUST equal the PLE control word sequence number. The control word sequence number MUST be generated per RFC 3550 Section 5.1 rules and MUST be incremented with every PLE packet sent.
PLE encapsulation consists of three layers stacked in order: PSN and VPWS demultiplexing headers (MPLS or SRv6), a PLE header (control word plus RTP header), and the bit-stream payload. The IWF is the functional block that encapsulates bit-streams into PLE packets and reverses the process.
Three new SRv6 'Endpoint with decapsulation and bit-stream cross-connect' behaviors are defined: End.DX1, End.DX1 with NEXT-CSID, and End.DX1 with REPLACE-CSID. They are variants of End.DX2: when the upper-layer header type is 147 (bit-stream), the outer IPv6 header and extensions are removed and the frame is forwarded to the associated CE-bound IWF.
Two new SRv6 encapsulation behaviors are defined: H.Encaps.L1 encapsulates a frame from an IWF in an IPv6 packet with an SRH (next header set to 147), and H.Encaps.L1.Red is an optimization that excludes the first SID from the SRH, placing it only in the IPv6 Destination Address field.
IANA assigned IP protocol number 147 (keyword BIT-EMU, 'Bit-stream Emulation') in the 'Assigned Internet Protocol Numbers' registry. This value is used in the IPv6 next header field or any extension header to indicate a bit-stream emulation payload; it is also valid as an IPv6 Extension Header indicator.
IANA assigned three new values in the 'SRv6 Endpoint Behaviors' registry: 158 (0x009E) for End.DX1, 159 (0x009F) for End.DX1 with NEXT-CSID, and 160 (0x00A0) for End.DX1 with REPLACE-CSID, all defined in RFC 9801.
A data-plane attack may force PLE packets to be dropped, reordered, or delayed beyond the de-jitter buffer limit, leading to degradation or service disruption; RFC 9055 (DetNet Security Considerations) is cited as a reference. PTP-based clock synchronization is also sensitive to PDV and vulnerable to threats outlined in RFC 7384.
Random initialization of sequence numbers in both the control word and the RTP header makes known-plaintext attacks more difficult. Misconnection detection using randomly chosen SSRC and/or PT values in the RTP header increases resilience to misconfiguration and some denial-of-service attacks.
The PSN (MPLS or SRv6) is assumed to be trusted and secure. Spoofed packets injected into the PSN can disrupt PLE service; this MUST be prevented by following best practices for PSN isolation as described in RFC 4381, RFC 5920, RFC 8402, and RFC 9252.
The CE-bound IWF operates in three states: (1) Intermediate — VPWS has just come up, packets are buffered and fault-indication signal is injected until the jitter buffer reaches a preconfigured fill level (typically 50%); (2) Normal — jitter buffer sufficiently filled, bit-stream is streamed out with egress clock recovery; (3) PLOS — consecutive packet loss exceeds 1 ms threshold, fault-indication injected and R bit signaled upstream. Transition from PLOS back to Normal requires the same preconfigured buffer fill as the Intermediate-to-Normal transition.
The DEG (Degradation) state is entered when the packet loss rate (PLR) exceeds a configurable SD threshold for a configurable number of consecutive 1-second intervals (default: PLR ≥ 15%, 7 consecutive intervals). ES-PLE, SES-PLE, and UAS-PLE performance counters are updated accordingly; UAS-PLE counting begins after 10 consecutive SES-PLEs by default.
The PLE Control Word is 4 bytes: bits 0–3 are 0000b (distinguishing it from IP/Ethernet), followed by L bit (attachment circuit fault), R bit (backward fault/packet-loss indication), 2 RSV bits, 2 FRG bits (always zero), 6-bit LEN field (always zero), and a 16-bit sequence number.
The RTP header (12 bytes, RFC 3550 format) immediately follows the PLE control word: V=2 (2 bits), P (1 bit, must be 0), X (1 bit, must be 0), CC (4 bits, must be 0), M (1 bit, must be 0), PT (7 bits, dynamic), 16-bit sequence number, 32-bit timestamp, and 32-bit SSRC.