Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) Circuit Emulation over Packet (CEP)
obsoletes
- rfc-5143 — Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) Circuit Emulation Service over MPLS (CEM) Encapsulation
Extracted elements (30)
B3 compensation is required for Line Terminating Equipment (LTE) implementations of fractional STS-1 or VC-4, since LTE does not terminate the path layer and must preserve end-to-end BIP-8 parity integrity across the PSN even after removing VT/VC columns. The compensation formula accounts for changes in both the current and previous frame to maintain correct BIP-8 parity.
Because of rate differences between VT and SPE levels, the VT EPAR packetizer converts multiple SPE pointer adjustments to fewer VT pointer adjustment indications using an accumulator algorithm. A VT pointer adjustment changes the accumulator by 783 units (one STS-1 SPE size), while an SPE pointer adjustment changes it by 1/4 of the VT size; this avoids the need for fractional adjustments at the VT layer.
A CEP pseudowire can be configured asymmetrically: one PE can use bandwidth reduction modes (DBA, fractional SPE) while the other sends the entire circuit unmodified. A PE that identifies such an asymmetric configuration based on comparing received CEP Options with its own configuration MAY report this to the operator but the pseudowire can still be established.
All CEP SPE implementations MUST support a packet size of 783 bytes and MAY support other packet sizes. VT emulation implementations MUST support payload size of one full VT super-frame and MAY support 1/2 and 1/4 VT super-frame payload sizes.
CEP PWs represent inelastic constant bit rate (CBR) flows and cannot respond to congestion in a TCP-friendly manner. CEP PWs SHOULD be carried across traffic-engineered PSNs providing bandwidth reservation, admission control, or forwarding prioritization (e.g., IntServ Guaranteed Service or DiffServ Expedited Forwarding). CEP PWs SHOULD monitor packet loss to detect severe congestion and SHOULD shut down bi-directionally if detected.
During AIS-P/V conditions, CEP packets are generated as usual with the L bit set to 1. The N and P bits SHOULD be set to 1 to indicate loss of pointer. If DBA is enabled, only the necessary headers (and optional padding) are transmitted, and the Length field MUST be set to the CEP header size plus RTP header size if used.
During negative pointer adjustment events, CEP implementations MUST include the H3 (or V3) byte in the SONET/SDH fragment; during positive pointer adjustment events, the stuff byte MUST be removed from the fragment. VT emulation implementations MUST NOT carry VT pointer bytes V1, V2, V3, and V4 as part of the CEP payload (except V3 during negative pointer adjustment).
For MPLS PSN transport, the bottom label in the MPLS label stack MUST be used to de-multiplex individual CEP channels (the PW Label). The CEP header follows the generic PWE3 Control Word format specified in PWE3-MPLSCW. Transport of CEP over non-MPLS PSNs is out of scope.
If the CEP de-packetizer encounters more than a configurable number of sequential empty packets, it MUST declare a Loss of Packet Synchronization (LOPS) defect. LOPS failure is declared after 2.5 ± 0.5 seconds of LOPS defect and cleared after 10 seconds free of LOPS defect state; the circuit is considered down while LOPS failure is active.
SONET/SDH fragments MUST be byte aligned with the SONET/SDH SPE or VT, with the first bit of each received byte placed as the Most Significant Bit of each fragment byte. Fragments MUST be constructed without knowledge or processing of any incidental payload scrambling.
The CEP de-packetizer MUST detect lost or misordered packets. It SHOULD play out an all-ones (AIS) pattern for dropped packets and SHOULD re-order out-of-order packets. If re-ordering is not supported, misordered packets MUST be dropped. The jitter buffer SHOULD be adjustable in length to account for varying network delay.
The CEP de-packetizer MUST play out one packet's worth of all ones for each received packet with the L bit set to 1, and MUST set the SONET/SDH Overhead to signal AIS-P/V. It MUST also play out AIS-P/V during loss of packet synchronization or upon receipt of CEP packets with both N and P bits set to 1 (LOP-P/V).
The CEP header L bit MUST be set to 1 to signal to the downstream PE that a failure condition (AIS-P/V) has been detected on the attachment circuit. The R bit MUST be set to 1 to signal loss of packet synchronization to the upstream PE, and MUST be cleared once packet synchronization is acquired.
The CEP packetizer MUST declare a circuit unequipped only if the Signal Label, Trace (J1/J2), and Tandem Connection (N1/N2/Z6) bytes all have zero value. During SPE/VT Unequipped, the SPE/VT MUST be transmitted into the packet network along with the appropriate headers, with N and P bits interpreted as usual.
The CEP Sequence Number field MUST continuously cycle from 0 to 0xFFFF following RTP rules. The Structure Pointer MUST contain the offset of the first byte of the SONET structure (J1 byte for SPE, V5 byte for VT) within the packet payload, and MUST be set to 0xFFF if the packet does not carry the J1 or V5 byte.
The CEP/TDM Bit Rate parameter is REQUIRED and MUST be set to the uncompressed payload data rate in 64-Kbps units (e.g., 26 for VT1.5/VC-11, 35 for VT2/VC-12, 783*N for STS-Nc). Attempts to establish a pseudowire between peers with different bit rates MUST be rejected with an incompatible bit rate status error code.
The PW Type field MUST be set to SONET/SDH Circuit Emulation over Packet (CEP). The control word is REQUIRED for CEP pseudowires; the C bit in PWid FEC and PW generalized ID FEC elements MUST be set. If the C bit is not set, the pseudowire MUST NOT be established and a Label Release MUST be sent with an Illegal C bit status code.
The RTP Version field MUST be set to 2; P, X, CC, and M bits MUST be set to 0 by the sender. The RTP Timestamp clock MUST be 19.44 MHz based on a local reference. The CEP receiver MUST sequence packets according to the CEP header Sequence Number and MAY verify correct sequencing using the RTP Sequence Number.
CEP defines three Near-End performance monitors: ES-CEP (Errored Seconds, containing at least one missing/dropped packet), SES-CEP (Severely Errored Seconds, containing buffer underrun/overrun, LOPS, or excessive missing packets), and UAS-CEP (Unavailable Seconds, declared after a configurable number of consecutive SES-CEP, default 10, and cleared after 10 consecutive seconds without SES-CEP).
Dynamic Bandwidth Allocation (DBA) is an OPTIONAL mechanism that suppresses transmission of the SPE/VT fragment payload when AIS-P/V or SPE/VT Unequipped conditions are detected. Implementations supporting DBA MUST include a per-channel mechanism to disable it for interoperability with non-DBA implementations. The packet transmission rate during DBA must remain equivalent to normal operation.
Explicit Pointer Adjustment Relay (EPAR) is an OPTIONAL mechanism to relay SONET/SDH pointer adjustment events across the PSN using the N and P bits of the CEP header. EPAR is only effective when both PW ends share a common timing reference; when N=0,P=1 indicates positive adjustment; N=1,P=0 indicates negative; N=1,P=1 indicates Loss of Pointer. Pointer adjustment events MUST be transmitted in three consecutive packets.
Fractional STS-1 (VC-3) encapsulation carries only selected VTs within an STS-1 container by removing fixed column bytes (columns 30 and 59) and bytes of unselected VTs. An optional 4-byte header extension adds a 28-bit Equipped Bit Mask (EBM) divided into 7 groups of 4 bits, one per VTG, where each bit indicates whether a specific VT is equipped and carried in the payload.
Fractional VC-4 encapsulation carries only selected VCs within a VC-4 container, removing fixed columns 2 and 3 of VC-4 and bytes of unselected VCs. An optional 12-byte header extension adds three 32-bit EBM words (one per TUG-3), each encoding 7 groups of 4 TUG-2 bits plus 2 bits (A=AIS, T=carried) for VC-3 within the TUG-3.
RTP header usage is OPTIONAL in CEP, providing timing information via the Timestamp field. When used, CEP employs RTP purely as a formal header reuse — RTP mechanisms such as RTCP, header compression, SRTP, extensions, CSRC lists, and padding are not applicable to pseudowires. The RTP timestamp clock frequency MUST be 19.44 MHz.
The basic CEP packet consists of (from outer to inner): PSN and Multiplexing Layer Headers, CEP Header, optional RTP Header (RFC 3550), and SONET/SDH Fragment. The SONET/SDH SPE or VT is broken into fragments, each prepended with a CEP header and optionally an RTP header, then carried over an MPLS PSN.
CEP encapsulation is subject to all general security considerations of PWE3-ARCH. The security of the transported CEP service is only as good as the security of the PSN, which may be less rigorous than native TDM due to inherent differences between circuit-switched and packet-switched networks. Although RTP may be optionally used, SRTP mechanisms are not a substitute for securing the PW and underlying MPLS network.
Packet synchronization has two states: synchronized and out-of-synchronization. Transition to synchronized requires playing out a configurable number of CEP packets with sequential sequence numbers. Loss of packet synchronization (LOPS) is declared after more than a configurable number of sequential empty packets; LOPS failure is declared after 2.5 ± 0.5 seconds of LOPS defect, and cleared after 10 seconds free of LOPS defect.
The CEP Header is a 64-bit (two 32-bit word) structure containing: 4 reserved zero bits, L (CEP-AIS), R (CEP-RDI), N and P (pointer adjustment), FRG (2 bits, must be 0), Length (6 bits), Sequence Number (16 bits), Reserved (20 bits), and Structure Pointer (12 bits). An optional 4-byte or 12-byte header extension carries the Equipped Bit Mask (EBM) for fractional encapsulations.
The CEP Options parameter is a REQUIRED 16-bit field containing: AIS (DBA on AIS), UNE (DBA on unequipped), RTP (RTP header used), EBM (EBM extension header used), 7 reserved bits, CEP Type (3 bits: 0x0=SPE, 0x1=VT, 0x2=Fractional SPE), and Async Type (2 bits: T3 and E3 bandwidth reduction flags). A PE that does not support a requested CEP option MUST send a label-release with CEP/TDM misconfiguration status.
The Extended Fractional STS-1 CEP Header adds a third 32-bit word to the basic CEP header: 4 reserved zero bits followed by a 28-bit Equipped Bit Mask (EBM). The EBM encodes 7 VTGs (4 bits each), where bit semantics depend on VT type: all 4 bits for VT1.5, first 3 bits for VT2, first 2 bits for VT3, and the rightmost bit for VT6.