PPP over SONET/SDH

Payload scrambling using X^43+1 was added (replacing RFC 1619) because RFC 1619 was operationally found to permit malicious users to generate packets with bit patterns that could create SONET/SDH-layer low-transition-density synchronization problems, emulate the SDH set-reset scrambler pattern, and replicate the STM-N frame alignment word.

security

The scrambler's initial seed is randomly chosen by the transmitter to improve operational security. This means the odds of an attacker guessing the scrambler state are 1/2^43, with an additional 1/127 probability of correct frame alignment, yielding approximately 9e-16 probability of deliberately causing SONET/SDH-layer problems.

security, crypto

The X^43+1 self-synchronous scrambler was chosen because it is the same scrambler used for ATM over SONET/SDH, and public network carriers have considerable operational experience with it.

For backwards compatibility with RFC 1619 (STS-3c-SPE/VC-4 only), a scrambler MAY have an on/off capability where the scrambler is bypassed entirely when off. If provided, the default MUST be scrambling enabled. When scrambling is off, Path Signal Label C2 is set to 207 (0xCF) instead of 22 (0x16).

For STS-12c-SPE/VC-4-4c and above, Address and Control Field Compression and Protocol Field Compression are NOT RECOMMENDED. The Magic Number option remains RECOMMENDED.

For STS-3c-SPE/VC-4, the Magic Number, No Address and Control Field Compression, and No Protocol Field Compression LCP configuration options are RECOMMENDED.

If a scrambler on/off capability is provided for backwards compatibility with RFC 1619, the default MUST be set to scrambling enabled.

security

The 32-bit FCS MUST be used for all SONET/SDH rates, with the sole exception that for STS-3c-SPE/VC-4 only, the 16-bit FCS MAY be used (though 32-bit is RECOMMENDED). The FCS length is set by provisioning and is not negotiated.

The Multiframe Indicator (H4) is unused and MUST be zero.

PPP frames are located by row within the SONET STS-SPE/SDH Higher Order VC payload. Because frames are variable in length, they are allowed to cross SONET STS-SPE/SDH Higher Order VC boundaries.

The only supported SONET/SDH SPE/VCs for PPP encapsulation are STS-3c-SPE (VC-4), STS-12c-SPE (VC-4-4c), STS-48c-SPE (VC-4-16c), and STS-192c-SPE (VC-4-64c).

The Path Signal Label (C2) is set to 22 (0x16) to indicate PPP with X^43+1 scrambling. For backwards compatibility with RFC 1619, when scrambling is off, the value 207 (0xCF) is used to indicate PPP without scrambling.

A known security issue is bandwidth reduction by intentional transmission of characters or sequences requiring transparency processing. A user may cause up to a 100% increase in bandwidth by filling packets with flag and/or escape characters.

security

Without payload scrambling (as in RFC 1619), malicious users could generate bit patterns causing SONET/SDH-layer low-transition-density synchronization problems, emulation of the SDH set-reset scrambler pattern, and replication of the STM-N frame alignment word. The X^43+1 scrambler was introduced to address these threats.

security

The transmit processing order is: IP -> PPP -> FCS generation -> Byte stuffing -> Scrambling -> SONET/SDH framing. The receive order is the reverse: SONET/SDH framing -> Descrambling -> Byte destuffing -> FCS detection -> PPP -> IP.

The octet stream is mapped into the SONET STS-SPE/SDH Higher Order VC with octet boundaries aligned with VC octet boundaries. The entire SONET/SDH payload (STS-SPE/Higher Order VC minus path overhead and fixed stuff) is scrambled using a self-synchronous scrambler of polynomial X^43+1.

The scrambler operates continuously through the bytes of the SONET STS-SPE/SDH Higher Order VC, bypassing path overhead and fixed stuff bytes. It is not reset per frame; state carries over from one VC to the next. The first 43 bits after startup or reframe will not be descrambled correctly.

The X^43+1 scrambler uses a 43-bit shift register XORed with the data stream. Scrambling is performed most-significant bit first (A[7], A[6], ... A[0], B[7], ...), which is opposite to the HDLC FCS bit order (least significant bit first).